CV

Education & Training

• Stanford University, Stanford, CA, USA (2022 – present)
  • Postdoctoral Scholar in Electrical Engineering
  • Advisor: Prof. Subhasish Mitra
• Massachusetts Institute of Technology, Cambridge, MA, USA (2018 – 2022)
  • Ph.D. in Electrical Engineering & Computer Science
  • Advisor: Prof. Max M. Shulaker
  • Thesis Title: Nanosystems: From the Lab to the Fab
  • Dissertation Committee: Prof. Max M. Shulaker, Prof. Jesús A. del Alamo, Prof. Akintunde Akinwande
  • Minor: Digital Image Processing
• Massachusetts Institute of Technology, Cambridge, MA, USA (2016 – 2018)
  • S.M. in Electrical Engineering & Computer Science
  • Advisor: Prof. Max M. Shulaker
  • Thesis Title: Energy efficient computing: from nanotubes to negative capacitance
• Indian Institute of Technology Kharagpur, Kharagpur, WB, India (2012 – 2016)
  • B.Tech. (Hons.) in Electronics & Electrical Communication Engineering
• Vivekananda Siksha Niketan High School, Bankura, WB, India
  • West Bengal Council of Higher Secondary Education - 12th Grade Examination (WBCHSE) (2012)
  • West Bengal Board of Secondary Education (WBBSE) - 10th Grade Examination (2010)

Research experience

• New Computing System Architectures Leveraging New Nanotechnologies
  • Led development and tape-out for first Monolithic 3D (M3D) IC from foundry leveraging Carbon Nanotube FETs (CNFETs), Resistive RAM (RRAM), and silicon, targeting 5-10× EDP benefit vs. iso-design-footprint and iso-memory-capacity 2D silicon-only ICs (DATE 2023)
  • Demonstrated first iso-footprint, iso-performance CNFET-RRAM memory stack compared to Si-RRAM memory stack compared at the same node measured from the same wafers from the same foundry (VLSI 2023, technology focus session)
• Emerging Nanomaterials and Nanodevices
  • Led development and optimization efforts for CNFET process
    • Back-gate CNFET CMOS (TNANO, 2018, ACS Nano 2018) which enabled the first CNFET RISC-V microprocessor (Nature 2019)
    • High-volume extraction of 99.99% pure semiconducting carbon nanotubes (CNTs) to meet carbon nanotube FET (CNFET) VLSI target (Advanced Electronic Materials 2022) and compatibility with silicon CMOS foundries
• Fab Integration: Led transition of CNFET process from “lab” to multiple commercial “fabs”
  • First commercial CNFET process: Integration of CNFET process at Analog Devices Inc. (ADI), Wilmington, MA (Nature Electronics 2020, EE Times, MIT News, Scitech Daily, EurekAlert) for research and development of future products (incorporated within ADI’s technology roadmap)
  • First foundry CNFET process leveraging key advances such as liftoff free CNFET CMOS (VLSI TSA 2022, EDL 2022 - editor’s pick), CNFET CMOS (Nature Electronics 2020), and M3D integration of multi-tier CNFET CMOS logic and RRAM at SkyWater (VLSI 2020 – joint technology and circuits focus, IEEE Spectrum, Business Wire)
• Applications: First application-level demonstrations of CNFET CMOS M3D technology
  • First M3D CNFET CMOS IC: 3D Imager integrating two tiers of CMOS CNFETs over Si photodetectors to perform real-time edge-detection (VLSI 2019, technology highlight + demo)

Service

Reviewer:

• IEEE Electron Device Letters (EDL)
• IEEE Transactions on Electron Devices (TED)
• IEEE Transactions on Circuits and Systems II: Express Briefs (TCAS2)
• Applied Physics Letters (APL)
• IEEE Access
• IEEE ISCAS Conference
• IEEE Transactions on Very Large Scale Integration Systems (TVLSI)

Outreach

EECS Graduate Application Assistance Program (GAAP) mentor, MIT (2020 - 2021)

• A program established to help potential PhD applicants from underrepresented minorities
• Mentored 9 students from 5 different countries

Member of the National Service Scheme, IIT Kharagpur (2012-2014)

• Substitute high-school English instructor in Balarampur, a remote village with economic constraints
• Ran a yearly food and clothes collection and distribution program