Tathagata Srimani

Tathagata Srimani

Assistant Professor, Electrical and Computer Engineering, Carnegie Mellon University

Tathagata Srimani

Tathagata Srimani is an assistant professor in the Department of Electrical and Computer Engineering, Carnegie Mellon University, Pittsburgh, where he leads the NEXUS Research Group (NEXUS: Nanoelectronics EXpeditions for Ubiquitous Systems). Previously, he was a postdoctoral scholar in the Department of Electrical Engineering at Stanford University. He received the S.M. and the Ph.D. degree in EECS from Massachusetts Institute of Technology in 2018 and 2022 respectively, and the B.Tech degree in E&ECE from Indian Institute of Technology, Kharagpur in 2016. His research interests include demonstrations of circuits and systems leveraging new nanotechnologies, heterogeneous 3D integration, and technology-application-architecture co-design.

His research results include the first silicon fab-compatible process for complementary Carbon Nanotube FETs (CNFETs) (IEEE TNANO 2018, ACS Nano 2018) which enabled the first CNFET RISC-V microprocessor (Nature 2019), and the first monolithic 3D system that integrates complementary CNFETs with silicon (IEEE Symp. VLSI Tech. 2019, Technology Highlight and Demo Session).

His work led to the transition of the first CNFET and CNFET + Resistive RAM (RRAM) ultra-dense (monolithic) 3D process in industrial silicon “fabs”: Analog Devices (Nature Electronics 2020) where active product development is underway, and at SkyWater Foundry (IEEE Symp. VLSI 2020, Joint Technology and Circuits Focus Session & IEEE Symp. VLSI Tech. 2023, Technology Focus Session and Best Student Paper) where CNFETs and RRAM are integrated at a 90nm node on 200mm silicon wafers as a foundry monolithic 3D technology (highlighted in President’s 2024 Nanotechnology Budget Report). Following extensive fabrication and design advances, this CNFET + RRAM monolithic 3D stack can now achieve comparable performance (read power, write energy/latency, endurance, retention, multiple bits-per-cell) in the same footprint as conventional Front-End-of-Line silicon FET + RRAM stack fabricated on the same wafers, from the same foundry, at the same node (IEEE Symp. VLSI Tech. 2023). Such CNFET+RRAM technology unlocks a large architecture design space with significant system-level energy-delay product (EDP) benefits(DATE 2023).

He was a recipient of the MIT Presidential Fellowship in 2016 and Morris Joseph Levin Award—best Masterworks (S.M. thesis) presentation at MIT in 2018.

Research Areas

  • New Nanomaterials and Device Concepts
  • New Logic and Memory Technologies
  • New Packaging and Integration Techniques
  • Nanofabrication Innovation
  • Integrated Micro/Nano Systems
  • Digital VLSI and Computer Systems Architecture
  • Technology-Architecture-Application Co-Design

Prospective Students

I will be looking for Ph.D. students starting Spring 2024. Please consider applying to CMU ECE!